About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

• IP/SOC/ASIC DV engineer responsible for planning and coordinating the design verification, and evaluation in high-speed data communication ICs. The candidate will work closely with digital design, design verification, firmware, and analog design engineers to ensure that projects are completed on time and in high quality.

• The responsibilities include but are not limited to.

• Lead the development and execution of IP/SOC/ASIC DV plans

• Understand and improve the unique in-house DV methodology and flow.

• Provide support to the product teams for both pre and post silicon.

• Develop and maintain relationships with key stakeholders.

• Identify and mitigate risks to project success.

• Continuously improve project execution processes

What We're Looking For

Bachelor's degree in computer science, Electrical Engineering or related fields and 5-15 years of related professional experience.
Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.

Good personal communication skills and team working spirit.

Hardworking and motivated to be part of a highly competent design verification team.

Must be proficient in the following skills:

• Fundamental concepts in digital logic design

• Understand IP/SOC/ASIC verification flows and methodologies

• Strong verification knowledge and hands on experience with SystemVerilog and UVM

• DV test plan, coverage driven constraints randomization testing

• Excellent cross-discipline communication and interpersonal skills

• Ability to work independently and as part of a team

• Strong problem-solving and decision-making skills

Highly desirable skills:

• Ethernet PHY, MAC, Interoperability, Clauses CL72/92/136/162, Serdes 112G/224G per lane

• Working with vendor Ethernet VIP's and testsuites

• Formal verification

• High Speed PHYs

• MATLAB and C/C++ based system simulation and evaluation, Systems C, DPI/PLI

• DSP function hardware implementation knowledge

• Python/Perl

#LI-RS1

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .