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About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
In this position, you will join Marvell CE AMS-IP DSP architecture team to contribute to state-of-the-art high-speed SerDes IPs used in a variety of products for the hyperscale could data center applications. You will participate in the verification, and optimization algorithms for PCIe and Ethernet solutions for 100G+ and 200G per lane data rates. You will be exposed to many technologies, including 5nm, 3nm, and 2nm developments, that span switch, PHY, compute, 5G baseband, cloud data center, and custom ASIC programs.What You Can Expect
- Create DSP and FEC hardware block specifications appropriate for RTL implementation.
- Collaborate with analog and digital team to understand architecture and implementation constraints.
- Write DSP algorithm specification and provide the algorithm in C/C++ or Python.
- Work with digital team/firmware team to implement DSP algorithm in hardware/firmware.
- Hands-on involvement in post-silicon performance tuning and optimization.
- Provide guidance on test plans for lab characterization.
- Provide support for internal/external customers deploying SerDes IPs.
What We're Looking For
Minimum Qualifications:
Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience with DSP architectures and algorithm development.
Preferred Qualifications:
- Deep understanding of digital communication and signal processing theory, including channel equalization, timing recovery, detection, and estimation.
- Experience with FEC (RS, BCH, soft decoding) is a plus.
- Experience with high-speed wireline transceiver using analog-based and ADC-based architecture is a big plus.
- Good programming skills in C/C++, Python or MATLAB.
- Knowledge of Ethernet, PCIE, CPRI standards is a plus.
- Work experience with high-speed SerDes (NRZ, PAM4) and understanding of analog circuit is a plus.
- Team player who is willing to take on a variety of projects, and self-motivated.
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Expected Base Pay Range (USD)
122,820 - 184,000, $ per annumThe successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .