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About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Built on decades of expertise and execution, Marvell's custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance chips.Our vision is to enable Compute & Storage solutions for AI, data center, and communication infrastructure.
What You Can Expect
In this hybrid role based in Santa Clara, you will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. Every day, you'll be working hands-on to triage workflows, whether you're running RTL code through synthesis and place and route (PnR) tools to create the physical view of the chip, analyzing performance by running timing analysis, verifying a robust power grid by performing EMIR analysis, especially on complex IP such as DDR, PCIe, etc.
- You will work closely with top level PD engineer, timing engineer, DFT engineer, and RTL designers.
- There are many sign-off checks that need to happen to verify that the database is ready to move on to the next level, and it's your responsibility to review completed runs for errors or create optimizations from successful runs.
- There are opportunities for potential customer interfacing.
What We're Looking For
Bachelor's degree in Computer Science, Electrical Engineering or related fields and 3+ years of related professional experience. OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2+ years of experience.
- Candidate should have good knowledge on PnR and have handled complex blocks using latest technology nodes like 7nm, 5nm, 3nm.
- Should have exposure in multiple tool usage across Cadence/Synopsys platforms, especially Innovus
- Knowledge of static timing analysis and synthesis
- Skilled knowledge on scripting language i.e. Python, Tcl, Perl
- Effective communication, verbal, and written skills
- Partition-level / multi-hierarchy experience is a plus
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Expected Base Pay Range (USD)
100,840 - 151,000, $ per annumThe successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .