Inbound activities Product collateral owner, generate white papers, applications notes, and apply project management processes to track progress. Collaborate with systems team to generate development board schematics, supervise layout review, and generate user manuals for development boards. Work on Proof of Concepts and applications of device features. Outbound activitie

Tactical execution of marketing functions such as forecasting, pricing, Inventory management, product life cycle management. Customized existing reports to assist Business Units managements for their Annual Operating Plan Track, analyses and collect information to assist on quarterly revenue achievements. Creating and management of SKUs in Marvell system for internal and

Electrical Engineer with experience in area of IP Design, characterization or quality/reliability.Experience with Supplier Management.Will work with 3rd party IP suppliers to ensure high quality IP deliverables to Marvell. Coordinate and drive Design Methodology reviews, reliability reviews, and SiReport reviews. Work with Supplier to resolve gaps to Marvell specification

New silicon validation and third party solution characterization including system level testing (hands on testing) Debug and resolve issues quickly working with design and packaging teams Design evaluation schematics, board layout guidelines and work with HW teams on GUI developments Partner with internal and external customers to address their critical concerns such as t

Expert in layout design flow, floor planning and layout automation Experience with 2.5D package design and development like CoWoS S and CoWoS R Strong expertise in using IC package layout tools like Cadence APD or Mentor XPD Hands on experience with floor planning tools like Cadence OrbitIO or Synopsis 3DIC Knowledge of IC package layout best practices and requirements fo

Responsibilities Responsible for design, verification, implementation (ASIC) for high performance, physical layer, high speed wired data communication networks including relevant signal processing algorithms. Develop ASIC specification, architecture, and micro architecture for major functional blocks in complex SOC solutions, for implementation signal processing and commu

Job Responsibilities Understand the requirements of the product Develop key metric data gathering and reporting tools Design and develop the produc t using Python or other programming languages Document and present solutions to business and executive teams Requirements The ASIC Business Unit is looking for an intern to develop productivity tools to organize and report key

ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high speed data communication ICs. The candidate will be involved in engineering implementation spec writing from system requirements, RTL design, verification, synthesis, static timing analysis.The responsibilities include but not limited to. Improve the design methodology

Designing, debugging and correlating ATE HW and SW Work with senior engineers on making SW improvements that will improve ATE throughput Optimize firmware running on ATE Configuring and implementing DSP routines for cutting edge high speed 400G optical PHY products Requirements Minimum Requirements Candidate MUST be currently pursuing a BS/MS (preferred) degree in CS/EE o

Understanding the specification of the product and functional blocks Creating functional verification test plan Developing verification test bench components using UVM and SV Writing, simulating and debugging test cases Regression and coverage analysis Requirements Typically requires a Bachelor's degree in Computer Science, Electrical Engineering or related fields, or the

Understanding NAND, SSD, PCIe and NVMe technologies Developing and modeling storage architectures using C, C++ or Python. Evaluate architectures based on SSD performance and latency metrics Exercise SSD performance models using synthetic and real workload metrics Make recommendations on CPU, memory, interface, interconnect specifications based on architectural modeling Re

About the Position Do you love building elegant solutions to highly complex challenges? Come to Marvell and be at the center of forefront Si foundry engineering and manufacturing for Marvell's cloud optimized Si for data infrastructure that keeps the world running. As a member of Foundry Process Engineering (FPE) team within Foundry Technology organization under Central E

Marvell seeks a talented Embedded Firmware Engineer to join our energetic, customer focused team in Santa Clara, California. You will work closely with a hardware development team in implementing the embedded firmware and/or customer facing GUI/API that manages Marvell's Layer 2 PHY DSP devices.If selected, this role will be involved with Modular software architecture def

Work with Marvell verification engineers to find RTL design bugs at IP/SoC level by helping to write design verification test bench components and/or tests and help debug simulation failures Help write scripts to support design verification tasks As an intern, you will be working directly with a senior mentor engineer on a real block in one of our designs. This is a great

The Workplace Strategy & Experience, Global Director will develop strategies and implement world class programs to design and optimize the spaces and services for Marvell employees as we reimagine the future of work with an emphasis on employee health and wellbeing. This role is critical to driving our business, hybrid work culture, and sustainability goals across our por