ASIC design engineer responsible for the design, verification, and evaluation of digital circuits in high speed data communication ICs. The candidate will be involved in engineering implementation spec writing from system requirements, RTL design, verification, synthesis, static timing analysis. The responsibilities include but not limited to. Improve the design methodolo

In this exciting role, you will define new commands/features for existing and new products. Write detailed design specifications for cryptographic algorithms which can be used by the development team as a basis for implementing, testing, documenting, and certifying the features. Provide technical guidance on the security features to the engineering team while working on c

We're looking for a strong Software Engineer who can help us troubleshoot, and solve LiquidSecurity HSM product issues in a production environment. This ensures customer success by reducing the time to resolve customer or field reported issues by building systems and tools that solve issues as they surface.This team also finds opportunities to automate processes where and

The successful candidate would have good understanding of the usage of related analog IPs to be integrated to SOC. Good understanding of technologies and IP development process and methodology are required. Excellent interpersonal skills and communication skills are a must. Provide basic IP integration support to SOC including IP selection and IP placement with reference

Full program responsibility at all stages definition, planning, development, validation and delivery to customers. Manage programs from definitions stage, thru silicon design, silicon samples, system and SW integration, until getting the silicones and system to mass production status. Work at matrix organization in front of multiple cross functional teams with 100's engin

Engineer, Applications Responsible for bring up, debug and characterize silicon level Marvell's internal IPs such as High Speed SerDes, USB, PLL/DLL, ADC, etc. in various Marvell products. Evaluate and debug new features in PHY, develop driver firmware, collect performance data, and resolve application/production issues including SAS and PCIe products. Support internal So

Plan and Execute emulation testplan for our bleeding edge network switch products. Support team members in Emulation compilation/infra needs. Requirements Must Have 1. Expert in Emulation platforms like Cadence Z1/Z2, and associated infra development and support 2. Expert in Ethernet test platforms like Ixia, Xena or Spirent and associated infra development and support 3.

As a part of the DFT team the suitable candidate will work on all aspects of DFT in top notch Switch products DFT architecture and Testability strategy, Flow, Implementation, Verification and post Si bring up. You'll work closely with other DFT team members for DFT features Implementation, Integration and Verification in SoC. You will also have close interaction with Logi

This role will be critical to our mission by being responsible for establishing enterprise storage and backup infrastructure vision, technical strategy at enterprise level. This will be a hands on role, where the Sr. Storage & Backup Architect will design, architect, deploy and manage enterprise level storage and backup infrastructure solutions. You will be joining the ex

The Cloud Security Analyst leads the implementation and development of innovative security architectures for protecting data deployed into diverse types of public, private, and hybrid cloud solutions. This position will a dvocate a DevSecOps culture, leveraging automation to deliver secure cloud architecture and protect the global enterprise cloud environment by continuou

To develop FW and tools for Solid State Device application. Requirements Minimum Qualifications Candidate MUST be currently pursuing BS/MS degree in CE/EE or related technological fields 0 1 years of previous experience Preferred Qualifications Experience in Python/C++ programming, embedded systems Knowledge in computer architecture, RTOS Good problem solving and communic

This position in particular is focusing onflash controllerIP. The challenge of this position asSr. StaffEngineer is to have deep understanding ofNAND protocol and ourflash controllerIP architecture. Then you will need to join discussion session of architecturedefinition and come up with micro architecture based on that. Besides, you will also need to work on RTL implement

As a System Design Engineer , one will be involved in and responsible for Responsibilities Contribute as system engineering team, engage with functional teams such as digital, analog, firmware, to develop Marvell's next gen, high speed networking PHY Serdes IP/ICs. Work independently and collaboratively in post silicon validation team, to collect, analyze massive data fro

This position in particular is focusing onflash controllerIP. The challenge of this position asSr. StaffEngineer is to have deep understanding ofNAND protocol and ourflash controllerIP architecture. Then you will need to join discussion session of architecturedefinition and come up with micro architecture based on that. Besides, you will also need to work on RTL implement

Becomeamemberofaworld classdesignteam. Youwillhaveanopportunitytodesignthelatesthigh performanceSSD controller andothercriticalhigh speed interface designsforMarvell'scoreproducts.Allteammembersparticipateincircuitarchitecture,circuitimplementation,designreview,layout,andsiliconvalidationinthefollowingareas Develop next generation SSD/HDD controller utilizing advanced dig